Circuit extraction

Results: 32



#Item
21Signal integrity / Design closure / Static timing analysis / Timing closure / Delay calculation / Application-specific integrated circuit / Design flow / Clock distribution network / Parasitic extraction / Electronic engineering / Electronic design automation / Signoff

Datasheet PrimeTime Golden Timing Signoff Solution and Environment Overview

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Source URL: www.synopsys.com

Language: English - Date: 2015-02-18 15:15:31
22Electronic design automation / Integrated circuits / Electronic design / Parasitic extraction / Digital electronics / Signal integrity / Standard cell / Resistor / Integrated circuit design / Electronic engineering / Electronics / Electromagnetism

White Paper StarRCâ„¢ Custom: Next-Generation Modeling and Extraction Solution for Custom IC Designs May 2010

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Source URL: www.synopsys.com

Language: English - Date: 2014-11-07 14:32:52
23Integrated circuits / Parasitic extraction / Electronic design / Digital electronics / Signal integrity / Signoff / Application-specific integrated circuit / Integrated circuit design / SPICE / Electronic engineering / Electronic design automation / Electronics

White Paper Extraction Techniques for High-performance, High-capacity Simulation September 2009

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Source URL: www.synopsys.com

Language: English - Date: 2014-11-07 14:32:47
24Integrated circuits / Parasitic extraction / Standard cell / Electronic design automation / Circuit extraction / Electromagnetic field solver / Multi-core processor / System on a chip / Simucad / Electronic engineering / Electronics / Electronic design

White Paper StarRC Custom Rapid3D Extraction Next Generation High Performance 3D Fast Field Solver June 2010

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Source URL: www.synopsys.com

Language: English - Date: 2014-11-07 14:32:51
25Imaging / TRECVID / Video content analysis / Feature extraction / Closed-circuit television / Surveillance / Security / National security

Event Detection in Airport Surveillance The TRECVid 2008 Evaluation Jerome Ajot, Jonathan Fiscus, John Garofolo Martial Michel, Paul Over, Travis Rose, Mehmet Yilmaz NIST

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Source URL: www-nlpir.nist.gov

Language: English - Date: 2008-12-17 12:10:36
26Integrated circuits / Hillsboro /  Oregon / Synopsys / Electronic design automation / Physical design / Integrated circuit design / Parasitic extraction / Functional verification / Signoff / Electronic engineering / Electronics / Electronic design

Datasheet Memory Solution Overview Memory products are among the most

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Source URL: www.synopsys.com

Language: English - Date: 2014-11-07 12:43:58
27Multiple patterning / Signoff / Design rule checking / Standard cell / Parasitic extraction / Physical design / Application-specific integrated circuit / Synopsys / Integrated circuit design / Electronic engineering / Electronic design automation / Integrated circuits

White Paper Design Solutions for 20nm and Beyond June 2012

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Source URL: www.synopsys.com

Language: English - Date: 2014-11-07 12:41:40
28Signoff / Synopsys / Static timing analysis / Signal integrity / Electronic circuit simulation / Delay calculation / Logic simulation / Parasitic extraction / SPICE / Electronic engineering / Electronic design automation / Digital electronics

Datasheet NanoTime Transistor-level Static Timing Analysis Solution for Custom Designs Overview

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Source URL: www.synopsys.com

Language: English - Date: 2015-02-27 00:06:11
29Integrated circuits / Electronic design / Parasitic extraction / Electromagnetic field solver / Standard cell / Circuit extraction / Application-specific integrated circuit / Signoff / Synopsys / Electronic engineering / Electronic design automation / Electronics

Datasheet StarRC Parasitic extraction Overview

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Source URL: www.synopsys.com

Language: English - Date: 2015-02-18 15:15:32
30Electronic design / Integrated circuits / Digital electronics / Signal integrity / Static timing analysis / System on a chip / Parasitic extraction / Electronic circuit / MOS Technology SID / Electronic engineering / Electronics / Electronic design automation

PROJECT PROFILE 2A704: Robust design for efficient use of nanometre technologies (ROBIN) EDA FOR SOC DESIGN AND DFM

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Source URL: www.catrene.org

Language: English - Date: 2009-03-25 10:35:46
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